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| 31710hkim 20100223-s00011,s00012,s00013/n1809hkim/52709hkim no.a1417-1/54 http://onsemi.com semiconductor components industries, llc, 2013 july, 2013 LC75812PT overview the LC75812PT is 1/8, 1/9 duty dot matrix lcd display controllers/drivers that support the display of characters, numbers, and symbols. in addition to generating dot matrix lcd drive signals based on data transferred serially from a microcontroller, the LC75812PT also provide on-chip character display rom and ram to allow display systems to be implemented easily. these products also provide up to 3 general-purpose output ports and incorporate a key scan circuit that accepts input from up to 35 keys to reduce printed circuit board wiring. features ? key input function for up to 35 keys (a key scan is performed only when a key is pressed.) ? controls and drives a 5 7 or 5 8 dot matrix lcd. ? supports accessory display segment drive (up to 65 segments) ? display technique: 1/8 duty 1/4 bias drive (5 7 dots) 1/9 duty 1/4 bias drive (5 8 dots) ? display digits: 13 digits 1 line (5 7 dots), 12 digits 1 line (5 8 dots) ? display control memory cgrom: 240 characters (5 7 or 5 8 dots) cgram: 16 characters (5 7 or 5 8 dots) adram: 13 5 bits dcram: 52 8 bits ? instruction function display on/off control display shift function ? sleep mode can be used to reduce current drain. ? built-in display contrast adjustment circuit ? switching between key scan output and general-purpose output ports can be controlled with instructions. ? pwm output for adjusting the led backlight brightness ? the frame frequency of the common and segment output waveforms can be controlled by instructions. ? serial data control of switching between the rc oscilla tor operating mode and external clock operating mode. ? independent lcd driver block power supply v lcd ? a voltage detection type reset circuit is provided to initialize the ic and prevent incorrect display. ? the inh pin is provided. this pin turns off the display, disables key scanning, and forces the general-purpose output ports to the low level. ? rc oscillator circuit ordering number : ena1417b cmos ic 1/8, 1/9 duty dot matrix lcd display controllers/drivers wi th key input function ? ccb is on semiconductor? ?s original format. all addresses are managed by on semiconductor? for this format. ? ccb is a registered trademark of semiconductor components industries, llc.
LC75812PT no.a1417-2/54 specifications absolute maximum ratings at ta = 25 c, v ss = 0v parameter symbol conditions ratings unit v dd max v dd -0.3 to +4.2 maximum supply voltage v lcd max v lcd -0.3 to +11.0 v ce, cl, di, inh -0.3 to +4.2 v in 1 ce, cl, di, inh v dd =2.7 to 3.6v -0.3 to +6.5 v in 2 osc, ki1 to ki5, test -0.3 to v dd +0.3 input voltage v in 3 v lcd 1, v lcd 2, v lcd 3, v lcd 4 -0.3 to v lcd +0.3 v v out 1 do -0.3 to +6.5 v out 2 osc, ks1 to ks7, p1 to p3 -0.3 to v dd +0.3 output voltage v out 3 v lcd 0, s1 to s65, com1 to com9 -0.3 to v lcd +0.3 v i out 1 s1 to s65 300 a i out 2 com1 to com9 3 i out 3 ks1 to ks7 1 output current i out 4 p1 to p3 5 ma allowable power dissipation pd max ta=85 c 200 mw operating temperature topr -40 to +85 c storage temperature tstg -55 to +125 c allowable operating range at ta = -40 c to +85 c, v ss = 0v ratings parameter symbol conditions min typ max unit v dd v dd 2.7 3.6 v lcd when the display contrast adjustment circuit is used. 7.0 10.0 supply voltage v lcd v lcd when the display contrast adjustment circuit is not used. 4.5 10.0 v output voltage v lcd 0 v lcd 0 v lcd 4 +4.5 v lcd v v lcd 1 v lcd 1 3/4 (v lcd 0- v lcd 4) v lcd 0 v lcd 2 v lcd 2 2/4 (v lcd 0- v lcd 4) v lcd 0 v lcd 3 v lcd 3 1/4 (v lcd 0- v lcd 4) v lcd 0 input voltage v lcd 4 v lcd 4 0 1.5 v continued on next page. stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty. LC75812PT no.a1417-3/54 continued from preceding page. ratings parameter symbol conditions min typ max unit ce, cl, di, inh 0.8v dd 3.6 v ih 1 ce, cl, di, inh v dd =2.7 to 3.6v 0.8v dd 5.5 v ih 2 osc external clock operating mode 0.8v dd v dd input high level voltage v ih 3 ki1 to ki5 0.6v dd v dd v v il 1 ce, cl, di, inh , ki1 to ki5 0 0.2v dd input low level voltage v il 2 osc external clock operating mode 0 0.2v dd v output pull-up voltage v oup do 0 5.5v recommended external resistor for rc oscillation rosc osc rc oscillator operating mode 10 k recommended external capacitor for rc oscillation cosc osc rc oscillator operating mode 470 pf guaranteed range of rc oscillation fosc osc rc oscillator operating mode 150 300 600 khz external clock operating frequency f ck osc external clock operating mode [figure 4] 100 300 600 khz external clock duty cycle d ck osc external clock operating mode [figure 4] 30 50 70 % data setup time tds cl, di [figure 2],[figure 3] 160 ns data hold time tdh cl, di [figure 2],[figure 3] 160 ns ce wait time tcp ce, cl [figure 2],[figure 3] 160 ns ce setup time tcs ce, cl [figure 2],[figure 3] 160 ns ce hold time tch ce, cl [figure 2],[figure 3] 160 ns high level clock pulse width t h cl [figure 2],[figure 3] 160 ns low level clock pulse width t l cl [figure 2],[figure 3] 160 ns do output delay time tdc do r pu =4.7k c l =10pf *1 [figure 2],[figure 3] 1.5 s do rise time tdr do r pu =4.7k c l =10pf *1 [figure 2],[figure 3] 1.5 s note: * 1. since the do pin is an open-drain output, these times depend on the values of the pull-up resistor r pu and the load capacitance c l . electrical characteristics for the allowable operating ranges ratings parameter symbol pins conditions min typ max unit hysteresis v h ce, cl, di, inh , ki1 to ki5 0.1v dd v power-down detection voltage v det 2.0 2.2 2.4 v v i =3.6v 5.0 i ih 1 ce, cl, di, inh v i =5.5v v dd =2.7 to 3.6v 5.0 input high level current i ih 2 osc v i =v dd external clock operating mode 5.0 a i il 1 ce, cl, di, inh v i =0v -5.0 input low level current i il 2 osc v i =0v external clock operating mode -5.0 a input floating voltage v if ki1 to ki5 0.05v dd v pull-down resistance r pd ki1 to ki5 v dd =3.3v 50 100 250 k output off leakage current i offh do v o =5.5v 6.0 a v oh 1 s1 to s65 i o =-20 a v lcd 0-0.6 v oh 2 com1 to com9 i o =-100 a v lcd 0-0.6 v oh 3 ks1 to ks7 i o =-250 a v dd -0.8 v dd -0.4 v dd -0.1 output high level voltage v oh 4 p1 to p3 i o =-1ma v dd -0.9 v v ol 1 s1 to s65 i o =20 a v lcd 4+0.6 v ol 2 com1 to com9 i o =100 a v lcd 4+0.6 v ol 3 ks1 to ks7 i o =12.5 a 0.1 0.4 1.2 v ol 4 p1 to p3 i o =1ma 0.9 output low level voltage v ol 5 do i o =1ma 0.1 0.3 v continued on next page. LC75812PT no.a1417-4/54 continued from preceding page. ratings parameter symbol pins conditions min typ max unit v mid 1 s1 to s65 i o = 20 a 2/4 (v lcd 0 -v lcd 4) -0.6 2/4 (v lcd 0 -v lcd 4) +0.6 v mid 2 com1 to com9 i o = 100 a 3/4 (v lcd 0 -v lcd 4) -0.6 3/4 (v lcd 0 -v lcd 4) +0.6 output middle level voltage *2 v mid 3 com1 to com9 i o = 100 a 1/4 (v lcd 0 -v lcd 4) -0.6 1/4 (v lcd 0 -v lcd 4) +0.6 v oscillator frequency fosc osc rosc=10k , cosc=470pf 210 300 390 khz i dd 1 v dd sleep mode 100 i dd 2 v dd v dd =3.6v, output open, fosc=300khz 500 1000 i lcd 1 v lcd sleep mode 15 i lcd 2 v lcd v lcd =10.0v, output open, fosc=300khz, when the display contrast adjustment circuit is used. 450 900 current drain i lcd 3 v lcd v lcd =10.0v, output open, fosc=300khz, when the display contrast adjustment circuit is not used. 200 400 a note: * 2. excluding the bias voltage generation divider resistor built into the v lcd 0, v lcd 1, v lcd 2, v lcd 3, and v lcd 4. (see figure 1.) excluding these resistors to the common and segment drivers [figure 1] v lcd v lcd 3 v lcd 4 v lcd 2 v lcd 0 v lcd 1 contrast adjuster LC75812PT no.a1417-5/54 (1) when cl is stopped at the low level (2) when cl is stopped at the high level [figure 3] (3) osc pin clock timing in external clock operating mode tdh 50% v ih 1 v ih 1 v il 1 v il 1 v ih 1 v il 1 tdr tdc tch tcs tcp tds cl t [figure 2] 50% v ih 1 tdh v ih 1 v il 1 v ih 1 v il 1 tdr tdc tch tcs tcp tds cl t [figure 4] v ih 2 v il 2 osc t ck l t ck h f ck = [khz] d ck = t ck h t ck h + t ck l 100[%] 50% 1 t ck h + t ck l LC75812PT no.a1417-6/54 package dimensions unit : mm (typ) 3274 pin assignments sanyo : tqfp100(14x14) 100 125 26 50 51 75 76 14.0 (1.0) (1.0) 0.1 0.125 16.0 0.2 0.5 1.2max 0.5 14.0 16.0 s55 s51 s52 s53 s54 s56 s57 s58 s59 s60 s61 s62 s63 s64 s65/com9 com8 com7 com6 com5 com4 com3 com2 com1 ks1/p1 ks2/p2 s5 s11 s4 s3 s2 s1 ks4 ks6 ks5 ki1 ks3 LC75812PT (tqfp100) ki2 ki3 ki4 p3/ks7 ki5 v lcd v dd v lcd 0 v lcd 2 v lcd 1 v lcd 4 v lcd 3 v ss osc test inh ce do cl s35 s34 s33 s32 s31 s29 s30 s27 s28 s26 di 51 75 50 76 26 100 25 1 s10 s9 s8 s7 s6 s16 s22 s15 s14 s13 s12 s21 s20 s19 s18 s17 s25 s24 s23 s40 s39 s38 s37 s36 s45 s44 s43 s42 s41 s50 s49 s48 s47 s46 top view LC75812PT no.a1417-7/54 block diagram s65/com9 s64 adram 65 bits cgram 5 8 16 bits vdet clock generator contrast adjuster timing generator address register instruction register common driver instruction decoder address counter dcram 52 8 bits cgrom 5 8 240 bits shift register latch segment driver osc inh do di p1/ks1 p2/ks2 ks3 ks6 ce ki1 ki2 ki3 ki4 ki5 cl s1 s63 com8 com1 key buffer ccb interface key scan v dd v lcd 4 v lcd3 v lcd 2 v lcd 1 v lcd v lcd 0 v ss test general purpose port p3/ks7 ks4 ks5 LC75812PT no.a1417-8/54 pin functions pin pin no. function active i/o handling when unused s1 to s64 s65/com9 1 to 64 65 segment driver outputs. s65/com9 can be used as common driver output pin under the "set display technique" instruction. - o open com1 to com8 73 to 66 common driver outputs. - o open ks1/p1 ks2/p2 ks3 to ks6 ks7/p3 74 75 76 to 79 85 key scan outputs. although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced cm os transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. ks1/p1, ks2/p2, and ks7/p3 can be used as general-purpose output ports under the "set key scan output port/general-purpose output port state" instruction. - o open ki1 to ki5 80 to 84 key scan inputs. these pins have built-in pull-down resistors. h i gnd osc 95 oscillator connections. an oscillator circuit is formed by connecting an external resistor and capacitor to this pin. this pin can also be used as the external clock input pin with the "set display technique" instruction. - i/o v dd ce 98 h i cl 99 i di 100 - i gnd do 97 serial data interface connections to the controller. note that do, being an open-drain output, requires a pull-up resistor. ce: chip enable cl: synchronization clock di: transfer data do: output data - o open inh 96 input that turns the display off, disables key scanning, and forces the general-purpose output ports low. ? when inh is low (v ss ): ? display off s1 to s64=?l? (v lcd 4) s65/com9=?l? (v lcd 4) com1 to com8=?l? (v lcd 4) ? general-purpose output ports p1 to p3=low (v ss ) ? key scanning disabled: ks1 to ks7=low (v ss ) ? all the key data is reset to low. ? when inh is high (v dd ): ? display on ? the state of the pins as key scan output pins or general-purpose output ports can be set with the "set key scan output port/general-purpose output port state" instruction. ? key scanning is enabled. however, serial data can be transferred when the inh pin is low. l i v dd test 94 this pin must be connected to ground. - i - v lcd 0 88 lcd drive 4/4 bias voltage (high level) supply pin. the level on this pin can be changed by the displa y contrast adjustment circuit. however, (v lcd 0 - v lcd 4) must be greater than or equal to 4.5v. also, external power must not be applied to this pin since the pin circuit includes the display contrast adjustment circuit. - o open v lcd 1 89 lcd drive 3/4 bias voltage (middl e level) supply pin. this pin can be used to supply the 3/4 (v lcd - v lcd 4) voltage level externally. - i open v lcd 2 90 lcd drive 2/4 bias voltage (middl e level) supply pin. this pin can be used to supply the 2/4 (v lcd 0 - v lcd 4) voltage level externally. - i open continued on next page. LC75812PT no.a1417-9/54 continued from preceding page. pin pin no. function active i/o handling when unused v lcd 3 91 lcd drive 1/4 bias voltage (middl e level) supply pin. this pin can be used to supply the 1/4 (v lcd 0 - v lcd 4) voltage level externally. - i open v lcd 4 92 lcd drive 0/4 bias voltage (low level) supply pin. fine adjustment of the display cont rast can be implemented by connecting an external variable resistor to this pin. however, (v lcd 0 - v lcd 4) must be greater than or equal to 4.5v, and v lcd 4 must be in the range 0v to 1.5v, inclusive. - i gnd v dd 86 logic block power supply connection. provide a voltage of between 2.7 to 3.6v. - - - v lcd 87 lcd driver block power supply connection. provide a voltage of between 7.0 to 10.0v when the display contrast adjustment circuit is used and provide a voltage of between 4.5 to 10.0v when the circuit is not used. - - - v ss 93 power supply connection. connect to ground. - - - block functions ? ac (address counter) ac is a counter that provides the addresses used for dcram and adram. the address is automatically modified internally, and the lcd display state is retained. ? dcram (data control ram) dcram is ram that is used to store display data expres sed as 8-bit character codes. (these character codes are converted to 5 7 or 5 8 dot matrix character patterns using cgrom or cgram.) dcram has a capacity of 52 8 bits, and can hold 52 characters. the table below lists the corresponde nce between the 6-bit dcram address loaded into ac and the display position on the lcd panel. ? when the dcram address loaded into ac is 00h. display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 dcram address (hexadecimal) 00 01 02 03 04 05 06 07 08 09 0a 0b 0c however, when the display shift is performed by specifying mdata, the dcram address shifts as shown below. display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 dcram address (hexadecimal) 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d (shift left) display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 dcram address (hexadecimal) 33 00 01 02 03 04 05 06 07 08 09 0a 0b (shift right) note: * 3. the dcram address is expressed in hexadecimal. dcram address da0 da1 da2 da3 da4 da5 hexadecimal hexadecimal example: when the dcram address is 2eh. da0 da1 da2 da3 da4 da5 0 1 1 1 0 1 note: * 4. 5 7 dots ? ? ? ? ? 13th digit display 5 7 dots 5 8 dots ? ? ? ? ? 13th digit display 4 8 dots most significant bit msb least significant bit lsb LC75812PT no.a1417-10/54 ? adram (additional data ram) adram is ram that is used to store the ad ata display data. adram has a capacity of 13 5 bits, and the stored display data is displayed directly without the use of cgrom or cgram. the table below lists the correspondence between the 4-bit adram address loaded into ac and the display position on the lcd panel. ? when the adram address loaded into ac is 0h. (number of digit displayed: 13) display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 adram address (hexadecimal) 0 1 2 3 4 5 6 7 8 9 a b c however, when the display shift is performed by specifying adata, the adram address shifts as shown below. display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 adram address (hexadecimal) 1 2 3 4 5 6 7 8 9 a b c 0 (shift left) display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 adram address (hexadecimal) c 0 1 2 3 4 5 6 7 8 9 a b (shift right) note: * 5. the adram address is expressed in hexadecimal. adram address ra0 ra1 ra2 ra3 hexadecimal example: when the adram address is ah. ra0 ra1 ra2 ra3 0 1 0 1 note: * 6. 5 7 dots ? ? ? ? ? 13th digit display 5 dots 5 8 dots ? ? ? ? ? 13th digit display 4 dots ? cgrom (character generator rom) cgrom is rom that is used to generate the 240 kinds of 5 7 or 5 8 dot matrix character patterns from the 8-bit character codes. cgrom has a capacity of 240 40 bits. when a character co de is written to dcram, the character pattern stored in cgrom corr esponding to the character code is displayed at the position on the lcd corresponding to the dcram address loaded into ac. ? cgram (character generator ram) cgram is ram to which user programs can freely write arbitr ary character patterns. up to 16 kinds of 5 7 or 5 8 dot matrix character patterns can be stored. cgram has a capacity of 16 40 bits. most significant bit msb least significant bit l s b LC75812PT no.a1417-11/54 serial data input (1) when cl is stopped at the low level (2) when cl is stopped at the high level ? b0 to b3, a0 to a3: ccb address 42h ? d0 to d119: instruction data the data is acquired on the rising edge of the cl signal and latched on the falling edge of the ce signal. when transferring instruction data from the microcontroller, applica tions must assure that the time from the transfer of one set of instruction data until the next instruction data transfer is significantly longer than the instruction execution time. instruction data (up to 120 bits) d119 d118 d4 d3 d2 0 0 0 0 1 0 1 0 d0 d1 ce di do cl a3 a2 a1 a0 b3 b2 b1 b0 instruction data (up to 120 bits) d119 d118 d4 d3 d2 1 0 0 0 0 0 1 0 d0 d1 ce cl di do a3 a2 a1 a0 b3 b2 b1 b0 LC75812PT no.a1417-12/54 notes: * 7. be sure to execute the "set display technique" instruction first after power-on (v det -based system reset). note that the execu tion time of this first instruction is 108 s (fosc=300khz, f ck =300khz). * 8.when the sleep mode (sp = 1) is set, the execution time is 27 s (when fosc = 300khz, f ck = 300khz). * 9. the data format differs when the dcram data write instruction is executed in the normal increment mode (im1=1, im2=0) or in the super increment mode (im1=0, im2=1). note that the execution time for the dcram data write instruction executed in the super increment mode is ti s (fosc=300khz, f ck =300khz). (see the detailed descriptions.) * 10. the data format differs when the adram data write instruction is executed in the normal increment mode (im1=1, im2=0) or in the super increment mode (im1=0, im2=1). note that the execution time for the adram data write instruction executed in the super increment mode i s ti s (fosc=300khz, f ck =300khz). (see the detailed descriptions.) * 11. the execution times listed he re apply when fosc=300khz, f ck =300khz. the execution times differ when the os cillator frequency fosc or the external clock frequency f ck differs. example: when fosc = 210khz, f ck = 210khz 27 s = 39 s, 108 s = 155 s, ti s = ti 1.43 s instruction table x: don't care 300 210 300 210 300 210 set ac address display shift display on/off control set display technique *7 cd25 ? cd32 ad1 ad2 ad3 ad4 ad5 x x x ac0 ac1 ac2 ac3 ac4 ac5 ac6 ac7 ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 da0 da1 da2 da3 da4 da5 x x kc4 kc5 kc6 kc7 kp1 kp2 kp3 x ct0 ct1 ct2 ct3 x x x x dg9 dg10 dg11 dg12 dg13 x x x dg1 dg2 dg3 dg4 dg5 dg6 dg7 dg8 execution time *11 d116 d117 d118 d119 0 s 0 s 27 s 27 s 27 s 0 s/27 s *8 0 s/ 108 s *7 im1 im2 x x ra0 ra1 ra2 ra3 m a r/l x m a sc sp dt fc0 fc1 oc ctc x x x x x x x x x x x d104 d105 d106 d107 d108 d109 d110 d111 d96 d97 d98 d99 d100 d101 d102 d103 instruction dcram data write *9 adram data write *10 cgram data write set key scan output port/ general-purpose output port state set display contrast im1 im2 x x da0 da1 da2 da3 da4 da5 x x ra0 ra1 ra2 ra3 x x x x x x x x x x x x pc32 pf0 pf1 pf2 pf3 kc1 kc2 kc3 cd33 ? cd40 w34 w35 pc10?pc31 w22?w25?w33 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 d112 d113 d114 d115 d88?d93 d94 d95 d80?d85 d86 d87 d72?d77 d78 d79 cd17 ? cd24 d0?d56?d71 27 s/ti s *9 27 s/ti s *10 w10?w15 w20 w21 ? cd1?cd16 LC75812PT no.a1417-13/54 detailed instruction descriptions ? set display technique ... LC75812PT no.a1417-14/54 dg1 to dg13: specifies the display digit display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 display digit data dg1 dg2 dg3 dg4 dg5 dg6 dg7 dg8 dg9 dg10 dg11 dg12 dg13 for example, if dg1 to dg7 are 1, and dg8 to dg13 are 0, then display digits 1 to 7 will be turned on, and display digits 8 to 13 will be turned off (blanked). sc: controls the common and segment output pins sc common and segment output pin states 0 output of lcd drive waveforms 1 fixed at the v lcd 4 level (all segments off) note: * 15. when sc is 1, the s1 to s65 and com1 to com9 output pins are set to the v lcd 4 level, regardless of the m, a, and dg1 to dg13 data. sp: controls the normal mode and sleep mode sp mode 0 normal mode 1 sleep mode the common and segment pins go to the v lcd 4 level and the oscillator on the osc pin is stopped (although it operates during key scan operations) in rc oscillator operating mode (oc="0") and reception of the external clock is stopped (external clock is received during key scan operations) in external clock operating mode (oc="1"), to reduce current drain. although the "display on/off cont rol", "set display contrast" and "set key scan output port/general-purpose output port state" (disallowed to set pins p1 to p3 for pwm signal output and pin p3 for clock signal output) instructions can be executed in this mode, applications must return the ic to nor mal mode to execute any of t he other instruction setting. when the ic is in externa l clock operating mode, be sure to stop the external clock i nput after the lapse of the instruction execution time (27 s: f ck =300khz). ? display shift ... LC75812PT no.a1417-15/54 ? set ac address... LC75812PT no.a1417-16/54 notes: * 16. ? dcram data write method when im1 = 0, im2 = 0 ? dcram data write method when im1 = 1, im2 = 0 (instructions other than the ?dcram data write? instruction cannot be executed.) ? dcram data write method when im1 = 0, im2 = 1 ti=13.5 s( -1) (n=8m+16, m is an integer between 2 and 13 that is the number of character s written as dcram data.) for example when n= 32 bits (m=2): ti= 40.5 s (fosc=300khz, f ck =300khz) when n= 80 bits (m=8) : ti=121.5 s (fosc=300khz, f ck =300khz) when n=120 bits (m=13): ti=189.0 s (fosc=300khz, f ck =300khz) note that the instruction execution time of 27 s and ti values in s apply when fosc=300khz and f ck =300khz, and that these execution times will differ when the cr oscillator frequency fosc and external clock frequency f ck differ. dcram data write finishes dcram data write finishes dcram data write finishes dcram data write finishes instruction execution time (27 s) (1) (1) (1) ccb address ccb address ccb address ccb address 24 bit 24 bit 24 bit (1) ce di dcram 24 bit instruction execution time (27 s) instruction execution time (27 s) instruction execution time (27 s) dcram data write finishes (4) (3) (3) (3) (3) (2) di dcram ce instructions other than the ?dcram data write? instruction cannot be executed. ccb address ccb address ccb address ccb address ccb address ccb address 24 bit 8 bit 8 bit 8 bit 8 bit 16 bit instruction execution time (27 s) instruction execution time (27 s) instruction execution time (27 s) instruction execution time (27 s) instruction execution time (27 s) instruction execution time (27 s) dcram data write finishes dcram data write finishes dcram data write finishes dcram data write finishes dcram data write finishes dcram data write finishes instruction execution time (ti s) instruction execution time (ti s) instruction execution time (ti s) (5) (5) ccb address ccb address n bit n bit (5) ce di dcram n bit ccb address dcram data write finishes dcram data write finishes n 8 LC75812PT no.a1417-17/54 data format at (1) (24 bits) code d96 d97 d98 d99 d100 d101 d102 d103 d104 d105 d106 d107 d108 d109 d110 d111 d112 d113 d114 d115 d116 d117 d118 d119 ac0 ac1 ac2 ac3 ac4 ac5 ac6 ac7 da0 da1 da2 da3 da4 da5 x x 0 0 x x 0 1 0 1 x: don?t care data format at (2) (24 bits) code d96 d97 d98 d99 d100 d101 d102 d103 d104 d105 d106 d107 d108 d109 d110 d111 d112 d113 d114 d115 d116 d117 d118 d119 ac0 ac1 ac2 ac3 ac4 ac5 ac6 ac7 da0 da1 da2 da3 da4 da5 x x 1 0 x x 0 1 0 1 x: don?t care data format at (3) (8 bits) code d112 d113 d114 d115 d116 d117 d118 d119 ac0 ac1 ac2 ac3 ac4 ac5 ac6 ac7 data format at (4) (16 bits) code d104 d105 d106 d107 d108 d109 d110 d111 d112 d113 d114 d115 d116 d117 d118 d119 ac0 ac1 ac2 ac3 ac4 ac5 ac6 ac7 0 0 x x 0 1 0 1 data format at (5) (n bit) code dz dz+1 dz+2 dz+3 dz+4 dz+5 dz+6 dz+7 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? d88 d89 d90 d91 d92 d93 d94 d95 ac0 1 ac1 1 ac2 1 ac3 1 ac4 1 ac5 1 ac6 1 ac7 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ac0 m-1 ac1 m-1 ac2 m-1 ac3 m-1 ac4 m-1 ac5 m-1 ac6 m-1 ac7 m-1 code d96 d97 d98 d99 d100 d101 d102 d103 d104 d105 d106 d107 d108 d109 d110 d111 d112 d113 d114 d115 d116 d117 d118 d119 ac0 m ac1 m ac2 m ac3 m ac4 m ac5 m ac6 m ac7 m da0 1 da1 1 da2 1 da3 1 da4 1 da5 1 x x 0 1 x x 0 1 0 1 x: don?t care here, n=8m+16, z=104-8m (m is an inte ger between 2 and 13 that is the number of characters writte n as dcram data.) correspondence between the dcram address and the dcram data dcram address dcram data da0 1 to da5 1 ac0 1 to ac7 1 (da0 1 to da5 1 )+1 ac0 2 to ac7 2 (da0 1 to da5 1 )+2 ac0 3 to ac7 3 (da0 1 to da5 1 )+(m-3) ac0 m-2 to ac7 m-2 (da0 1 to da5 1 )+(m-2) ac0 m-1 to ac7 m-1 (da0 1 to da5 1 )+(m-1) ac0 m to ac7 m LC75812PT no.a1417-18/54 example 1: when n=32 bits (m=2: 2 characters dcram data write operation) code d88 d89 d90 d91 d92 d93 d94 d95 d96 d97 d98 d99 d100 d101 d102 d103 ac0 1 ac1 1 ac2 1 ac3 1 ac4 1 ac5 1 ac6 1 ac7 1 ac0 2 ac1 2 ac2 2 ac3 2 ac4 2 ac5 2 ac6 2 ac7 2 code d104 d105 d106 d107 d108 d109 d110 d111 d112 d113 d114 d115 d116 d117 d118 d119 da0 1 da1 1 da2 1 da3 1 da4 1 da5 1 x x 0 1 x x 0 1 0 1 x: don?t care correspondence between the dcram address and the dcram data dcram address dcram data da0 1 to da5 1 ac0 1 to ac7 1 (da0 1 to da5 1 )+1 ac0 2 to ac7 2 example 2: when n=80 bits (m=8: 8 characters dcram data write operation) code d40 d41 d42 d43 d44 d45 d46 d47 d48 d49 d50 d51 d52 d53 d54 d55 ac0 1 ac1 1 ac2 1 ac3 1 ac4 1 ac5 1 ac6 1 ac7 1 ac0 2 ac1 2 ac2 2 ac3 2 ac4 2 ac5 2 ac6 2 ac7 2 code d56 d57 d58 d59 d60 d61 d62 d63 d64 d65 d66 d67 d68 d69 d70 d71 ac0 3 ac1 3 ac2 3 ac3 3 ac4 3 ac5 3 ac6 3 ac7 3 ac0 4 ac1 4 ac2 4 ac3 4 ac4 4 ac5 4 ac6 4 ac7 4 code d72 d73 d74 d75 d76 d77 d78 d79 d80 d81 d82 d83 d84 d85 d86 d87 ac0 5 ac1 5 ac2 5 ac3 5 ac4 5 ac5 5 ac6 5 ac7 5 ac0 6 ac1 6 ac2 6 ac3 6 ac4 6 ac5 6 ac6 6 ac7 6 code d88 d89 d90 d91 d92 d93 d94 d95 d96 d97 d98 d99 d100 d101 d102 d103 ac0 7 ac1 7 ac2 7 ac3 7 ac4 7 ac5 7 ac6 7 ac7 7 ac0 8 ac1 8 ac2 8 ac3 8 ac4 8 ac5 8 ac6 8 ac7 8 code d104 d105 d106 d107 d108 d109 d110 d111 d112 d113 d114 d115 d116 d117 d118 d119 da0 1 da1 1 da2 1 da3 1 da4 1 da5 1 x x 0 1 x x 0 1 0 1 x: don't care correspondence between the dcram address and the dcram data dcram address dcram data da0 1 to da5 1 ac0 1 to ac7 1 (da0 1 to da5 1 )+1 ac0 2 to ac7 2 (da0 1 to da5 1 )+2 ac0 3 to ac7 3 (da0 1 to da5 1 )+3 ac0 4 to ac7 4 (da0 1 to da5 1 )+4 ac0 5 to ac7 5 (da0 1 to da5 1 )+5 ac0 6 to ac7 6 (da0 1 to da5 1 )+6 ac0 7 to ac7 7 (da0 1 to da5 1 )+7 ac0 8 to ac7 8 LC75812PT no.a1417-19/54 example 3: when n=120 bits (m=13: 13 characters dcram data write operation) code d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ac0 1 ac1 1 ac2 1 ac3 1 ac4 1 ac5 1 ac6 1 ac7 1 ac0 2 ac1 2 ac2 2 ac3 2 ac4 2 ac5 2 ac6 2 ac7 2 code d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 ac0 3 ac1 3 ac2 3 ac3 3 ac4 3 ac5 3 ac6 3 ac7 3 ac0 4 ac1 4 ac2 4 ac3 4 ac4 4 ac5 4 ac6 4 ac7 4 code d32 d33 d34 d35 d36 d37 d38 d39 d40 d41 d42 d43 d44 d45 d46 d47 ac0 5 ac1 5 ac2 5 ac3 5 ac4 5 ac5 5 ac6 5 ac7 5 ac0 6 ac1 6 ac2 6 ac3 6 ac4 6 ac5 6 ac6 6 ac7 6 code d48 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 ac0 7 ac1 7 ac2 7 ac3 7 ac4 7 ac5 7 ac6 7 ac7 7 ac0 8 ac1 8 ac2 8 ac3 8 ac4 8 ac5 8 ac6 8 ac7 8 code d64 d65 d66 d67 d68 d69 d70 d71 d72 d73 d74 d75 d76 d77 d78 d79 ac0 9 ac1 9 ac2 9 ac3 9 ac4 9 ac5 9 ac6 9 ac7 9 ac0 10 ac1 10 ac2 10 ac3 10 ac4 10 ac5 10 ac6 10 ac7 10 code d80 d81 d82 d83 d84 d85 d86 d87 d88 d89 d90 d91 d92 d93 d94 d95 ac0 11 ac1 11 ac2 11 ac3 11 ac4 11 ac5 11 ac6 11 ac7 11 ac0 12 ac1 12 ac2 12 ac3 12 ac4 12 ac5 12 ac6 12 ac7 12 code d96 d97 d98 d99 d100 d101 d102 d103 d104 d105 d106 d107 d108 d109 d110 d111 ac0 13 ac1 13 ac2 13 ac3 13 ac4 13 ac5 13 ac6 13 ac7 13 da0 1 da1 1 da2 1 da3 1 da4 1 da5 1 x x code d112 d113 d114 d115 d116 d117 d118 d119 0 1 x x 0 1 0 1 x: don't care correspondence between the dcram address and the dcram data dcram address dcram data dcram address dcram data da0 1 to da5 1 ac0 1 to ac7 1 (da0 1 to da5 1 )+7 ac0 8 to ac7 8 (da0 1 to da5 1 )+1 ac0 2 to ac7 2 (da0 1 to da5 1 )+8 ac0 9 to ac7 9 (da0 1 to da5 1 )+2 ac0 3 to ac7 3 (da0 1 to da5 1 )+9 ac0 10 to ac7 10 (da0 1 to da5 1 )+3 ac0 4 to ac7 4 (da0 1 to da5 1 )+10 ac0 11 to ac7 11 (da0 1 to da5 1 )+4 ac0 5 to ac7 5 (da0 1 to da5 1 )+11 ac0 12 to ac7 12 (da0 1 to da5 1 )+5 ac0 6 to ac7 6 (da0 1 to da5 1 )+12 ac0 13 to ac7 13 (da0 1 to da5 1 )+6 ac0 7 to ac7 7 LC75812PT no.a1417-20/54 ? adram data write ... LC75812PT no.a1417-21/54 notes: * 17. ? adram data write method when im1 = 0, im2 = 0 ? adram data write method when im1 = 1, im2 = 0 (instructions other than the ?adram data write? instruction cannot be executed.) ? adram data write method when im1 = 0, im2 = 1 ti=13.5 s( -1) (n=8m+16, m is an integer between 2 and 13 that is the number of character s written as adram data.) for example when n= 32 bits (m=2): ti= 40.5 s (fosc=300khz, f ck =300khz) when n= 80 bits (m=8): ti=121.5 s (fosc=300khz, f ck =300khz) when n=120 bits (m=13): ti=189.0 s (fosc=300khz, f ck =300khz) note that the instruction execution time of 27 s and ti values in s apply when fosc=300khz and f ck =300khz, and that these execution times will differ when the cr oscillator frequency fosc and external clock frequency f ck differ. adram data write finishes adram data write finishes adram data write finishes adram data write finishes instruction execution time (27 s) (6) (6) (6) ccb address ccb address ccb address ccb address 24 bit 24 bit 24 bit (6) ce di adram 24 bit instruction execution time ( 27 s) instruction execution time (27 s) adram data write finishes (9) (8) (8) (8) (8) (7) di adram ce instructions other than the ?adram data write? instruction cannot be executed. ccb address ccb address ccb address ccb address ccb address ccb address 24 bit 8 bit 8 bit 8 bit 8 bit 16 bit instruction execution time (27 s) instruction execution time (27 s) instruction execution time (27 s) instruction execution time (27 s) instruction execution time (27 s) instruction execution time (27 s) adram data write finishes adram data write finishes adram data write finishes adram data write finishes adram data write finishes adram data write finishes instruction execution time (ti s) instruction execution time (ti s) instruction execution time (ti s) (10) (10) ccb address ccb address n bit n bit (10) ce di adram n bit ccb address adram data write finishes adram data write finishes n 8 LC75812PT no.a1417-22/54 data format at (6) (24 bits) code d96 d97 d98 d99 d100 d101 d102 d103 d104 d105 d106 d107 d108 d109 d110 d111 d112 d113 d114 d115 d116 d117 d118 d119 ad1 ad2 ad3 ad4 ad5 x x x ra0 ra1 ra2 ra3 x x x x 0 0 x x 0 1 1 0 x: don?t care data format at (7) (24 bits) code d96 d97 d98 d99 d100 d101 d102 d103 d104 d105 d106 d107 d108 d109 d110 d111 d112 d113 d114 d115 d116 d117 d118 d119 ad1 ad2 ad3 ad4 ad5 x x x ra0 ra1 ra2 ra3 x x x x 1 0 x x 0 1 1 0 x: don?t care data format at (8) (8 bits) code d112 d113 d114 d115 d116 d117 d118 d119 ad1 ad2 ad3 ad4 ad5 x x x data format at (9) (16 bits) code d104 d105 d106 d107 d108 d109 d110 d111 d112 d113 d114 d115 d116 d117 d118 d119 ad1 ad2 ad3 ad4 ad5 x x x 0 0 x x 0 1 1 0 x: don?t care data format at (10) (n bit) code dz dz+1 dz+2 dz+3 dz+4 dz+5 dz+6 dz+7 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? d88 d89 d90 d91 d92 d93 d94 d95 ad1 1 ad2 1 ad3 1 ad4 1 ad5 1 x x x ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ad1 m-1 ad2 m-1 ad3 m-1 ad4 m-1 ad5 m-1 x x x code d96 d97 d98 d99 d100 d101 d102 d103 d104 d105 d106 d107 d108 d109 d110 d111 d112 d113 d114 d115 d116 d117 d118 d119 ad1 m ad2 m ad3 m ad4 m ad5 m x x x ra0 1 ra1 1 ra2 1 ra3 1 x x x x 0 1 x x 0 1 1 0 x: don?t care here, n=8m+16, z=104-8m (m is an integer between 2 and 13 that is the number of characters written as adram data.) correspondence between the adram address and theadram data adram address adram data ra0 1 to ra3 1 ad1 1 to ad5 1 (ra0 1 to ra3 1 )+1 ad1 2 to ad5 2 (ra0 1 to ra3 1 )+2 ad1 3 to ad5 3 (ra0 1 to ra3 1 )+(m-3) ad1 m-2 to ad5 m-2 (ra0 1 to ra3 1 )+(m-2) ad1 m-1 to ad5 m-1 (ra0 1 to ra3 1 )+(m-1) ad1 m to ad5 m LC75812PT no.a1417-23/54 example 1: when n=32 bits (m=2: 2 characters adram data write operation) code d88 d89 d90 d91 d92 d93 d94 d95 d96 d97 d98 d99 d100 d101 d102 d103 ad1 1 ad2 1 ad3 1 ad4 1 ad5 1 x x x ad1 2 ad2 2 ad3 3 ad4 4 ad5 5 xxx code d104 d105 d106 d107 d108 d109 d110 d111 d112 d113 d114 d115 d116 d117 d118 d119 ra0 1 ra1 1 ra2 1 ra3 1 x x x x 0 1 x x 0 1 1 0 x: don?t care correspondence between the adram address and the adram data adram address adram data ra0 1 to ra3 1 ad1 1 to ad5 1 (ra0 1 to ra3 1 )+1 ad1 2 to ad5 2 example 2: when n=80 bits (m=8: 8 characters adram data write operation) code d40 d41 d42 d43 d44 d45 d46 d47 d48 d49 d50 d51 d52 d53 d54 d55 ad1 1 ad2 1 ad3 1 ad4 1 ad5 1 x x x ad1 2 ad2 2 ad3 2 ad4 2 ad5 2 xxx code d56 d57 d58 d59 d60 d61 d62 d63 d64 d65 d66 d67 d68 d69 d70 d71 ad1 3 ad2 3 ad3 3 ad4 3 ad5 3 x x x ad1 4 ad2 4 ad3 4 ad4 4 ad5 4 xxx code d72 d73 d74 d75 d76 d77 d78 d79 d80 d81 d82 d83 d84 d85 d86 d87 ad1 5 ad2 5 ad3 5 ad4 5 ad5 5 x x x ad1 6 ad2 6 ad3 6 ad4 6 ad5 6 xx x code d88 d89 d90 d91 d92 d93 d94 d95 d96 d97 d98 d99 d100 d101 d102 d103 ad1 7 ad2 7 ad3 7 ad4 7 ad5 7 x x x ad1 8 ad2 8 ad3 8 ad4 8 ad5 8 xxx code d104 d105 d106 d107 d108 d109 d110 d111 d112 d113 d114 d115 d116 d117 d118 d119 ra0 1 ra1 1 ra2 1 ra3 1 x x x x 0 1 x x 0 1 1 0 x: don't care correspondence between the adram address and the adram data adram address adram data ra0 1 to ra3 1 ad1 1 to ad5 1 (ra0 1 to ra3 1 )+1 ad1 2 to ad5 2 (ra0 1 to ra3 1 )+2 ad1 3 to ad5 3 (ra0 1 to ra3 1 )+3 ad1 4 to ad5 4 (ra0 1 to ra3 1 )+4 ad1 5 to ad5 5 (ra0 1 to ra3 1 )+5 ad1 6 to ad5 6 (ra0 1 to ra3 1 )+6 ad1 7 to ad5 7 (ra0 1 to ra3 1 )+7 ad1 8 to ad5 8 LC75812PT no.a1417-24/54 example 3: when n=120 bits (m=13: 13 characters adram data write operation) code d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ad1 1 ad2 1 ad3 1 ad4 1 ad5 1 x x x ad1 2 ad2 2 ad3 2 ad4 2 ad5 2 xxx code d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 ad1 3 ad2 3 ad3 3 ad4 3 ad5 3 x x x ad1 4 ad2 4 ad3 4 ad4 4 ad5 4 xxx code d32 d33 d34 d35 d36 d37 d38 d39 d40 d41 d42 d43 d44 d45 d46 d47 ad1 5 ad2 5 ad3 5 ad4 5 ad5 5 x x x ad1 6 ad2 6 ad3 6 ad4 6 ad5 6 xxx code d48 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 ad1 7 ad2 7 ad3 7 ad4 7 ad5 7 x x x ad1 8 ad2 8 ad3 8 ad4 8 ad5 8 xxx code d64 d65 d66 d67 d68 d69 d70 d71 d72 d73 d74 d75 d76 d77 d78 d79 ad1 9 ad2 9 ad3 9 ad4 9 ad5 9 x x x ad1 10 ad2 10 ad3 10 ad4 10 ad5 10 xxx code d80 d81 d82 d83 d84 d85 d86 d87 d88 d89 d90 d91 d92 d93 d94 d95 ad1 11 ad2 11 ad3 11 ad4 11 ad5 11 xx x ad1 12 ad2 12 ad3 12 ad4 12 ad5 12 xxx code d96 d97 d98 d99 d100 d101 d102 d103 d104 d105 d106 d107 d108 d109 d110 d111 ad1 13 ad2 13 ad3 13 ad4 13 ad5 13 xx x ra0 1 ra1 1 ra2 1 ra3 1 xxxx code d112 d113 d114 d115 d116 d117 d118 d119 0 1 x x 0 1 1 0 x: don't care correspondence between the adram address and the adram data adram address adram data adram address adram data ra0 1 to ra3 1 ad1 1 to ad5 1 (ra0 1 to ra3 1 )+7 ad1 8 to ad5 8 (ra0 1 to ra3 1 )+1 ad1 2 to ad5 2 (ra0 1 to ra3 1 )+8 ad1 9 to ad5 9 (ra0 1 to ra3 1 )+2 ad1 3 to ad5 3 (ra0 1 to ra35 1 )+9 ad1 10 to ad5 10 (ra0 1 to ra3 1 )+3 ad1 4 to ad5 4 (ra0 1 to ra3 1 )+10 ad1 11 to ad5 11 (ra0 1 to ra3 1 )+4 ad1 5 to ad5 5 (ra0 1 to ra3 1 )+11 ad1 12 to ad5 12 (ra0 1 to ra3 1 )+5 ad1 6 to ad5 6 (ra0 1 to ra3 1 )+12 ad1 13 to ad5 13 (ra0 1 to ra3 1 )+6 ad1 7 to ad5 7 LC75812PT no.a1417-25/54 ? cgram data write ... LC75812PT no.a1417-26/54 ? set display contrast? LC75812PT no.a1417-27/54 ? set key scan output port/general-purpose output port state ... LC75812PT no.a1417-28/54 pf0 to pf3: set the frame frequency of the pwm output waveforms. (when general-purpose outout ports p1 to p3 are set to select the pwm signal generation function.) pf0 pf1 pf2 pf3 pwm output wave form frame frequency fp[hz] 0 0 0 0 fosc/1536, f ck /1536 1 0 0 0 fosc/1408, f ck /1408 0 1 0 0 fosc/1280, f ck /1280 1 1 0 0 fosc/1152, f ck /1152 0 0 1 0 fosc/1024, f ck /1024 1 0 1 0 fosc/896, f ck /896 0 1 1 0 fosc/768, f ck /768 1 1 1 0 fosc/640, f ck /640 0 0 0 1 fosc/512, f ck /512 1 0 0 1 fosc/384, f ck /384 0 1 0 1 fosc/256, f ck /256 w10 to w15, w20 to w25, w30 to w35: set the pulse width of the pwm output waveforms. (when general-purpose outout ports p1 to p3 are set to select the pwm signal generation function.) wn0 wn1 wn2 wn3 wn4 wn5 pwm signal pn pulse width wn0 wn1 wn2 wn3 wn4 wn5 pwm signal pn pulse width 0 0 0 0 0 0 (1/64) tp 0 0 0 0 0 1 (33/64) tp 1 0 0 0 0 0 (2/64) tp 1 0 0 0 0 1 (34/64) tp 0 1 0 0 0 0 (3/64) tp 0 1 0 0 0 1 (35/64) tp 1 1 0 0 0 0 (4/64) tp 1 1 0 0 0 1 (36/64) tp 0 0 1 0 0 0 (5/64) tp 0 0 1 0 0 1 (37/64) tp 1 0 1 0 0 0 (6/64) tp 1 0 1 0 0 1 (38/64) tp 0 1 1 0 0 0 (7/64) tp 0 1 1 0 0 1 (39/64) tp 1 1 1 0 0 0 (8/64) tp 1 1 1 0 0 1 (40/64) tp 0 0 0 1 0 0 (9/64) tp 0 0 0 1 0 1 (41/64) tp 1 0 0 1 0 0 (10/64) tp 1 0 0 1 0 1 (42/64) tp 0 1 0 1 0 0 (11/64) tp 0 1 0 1 0 1 (43/64) tp 1 1 0 1 0 0 (12/64) tp 1 1 0 1 0 1 (44/64) tp 0 0 1 1 0 0 (13/64) tp 0 0 1 1 0 1 (45/64) tp 1 0 1 1 0 0 (14/64) tp 1 0 1 1 0 1 (46/64) tp 0 1 1 1 0 0 (15/64) tp 0 1 1 1 0 1 (47/64) tp 1 1 1 1 0 0 (16/64) tp 1 1 1 1 0 1 (48/64) tp 0 0 0 0 1 0 (17/64) tp 0 0 0 0 1 1 (49/64) tp 1 0 0 0 1 0 (18/64) tp 1 0 0 0 1 1 (50/64) tp 0 1 0 0 1 0 (19/64) tp 0 1 0 0 1 1 (51/64) tp 1 1 0 0 1 0 (20/64) tp 1 1 0 0 1 1 (52/64) tp 0 0 1 0 1 0 (21/64) tp 0 0 1 0 1 1 (53/64) tp 1 0 1 0 1 0 (22/64) tp 1 0 1 0 1 1 (54/64) tp 0 1 1 0 1 0 (23/64) tp 0 1 1 0 1 1 (55/64) tp 1 1 1 0 1 0 (24/64) tp 1 1 1 0 1 1 (56/64) tp 0 0 0 1 1 0 (25/64) tp 0 0 0 1 1 1 (57/64) tp 1 0 0 1 1 0 (26/64) tp 1 0 0 1 1 1 (58/64) tp 0 1 0 1 1 0 (27/64) tp 0 1 0 1 1 1 (59/64) tp 1 1 0 1 1 0 (28/64) tp 1 1 0 1 1 1 (60/64) tp 0 0 1 1 1 0 (29/64) tp 0 0 1 1 1 1 (61/64) tp 1 0 1 1 1 0 (30/64) tp 1 0 1 1 1 1 (62/64) tp 0 1 1 1 1 0 (31/64) tp 0 1 1 1 1 1 (63/64) tp 1 1 1 1 1 0 (32/64) tp 1 1 1 1 1 1 (64/64) tp note: * 20. wn0 to wn5 (n=1 to 3): pwm data for the pwm output waveforms at general-purpose output ports pn (n=1 to 3). t p = 1 fp LC75812PT no.a1417-29/54 serial data output (1) when cl is stopped at the low level (2) when cl is stopped at the high level ? b0 to b3, a0 to a3: ccb address 43h ? kd1 to kd35: key data ? sa: sleep acknowledge data note: * 21. when key data read operation is executed with do set high (no key data read request present), the key data (kd1 to kd35) and sleep acknowledge data (sa) are invalid. output data (1) kd1 to kd35: key data when a key matrix of up to 35 keys is formed from the ks1 to ks7 output pins and the ki1 to ki5 input pins and one of those keys is pressed, the key output data corresponding to that key will be set to 1. the table shows the relationship between those pins and the key data bits. ki1 ki2 ki3 ki4 ki5 ks1/p1 kd1 kd2 kd3 kd4 kd5 ks2/p1 kd6 kd7 kd8 kd9 kd10 ks3 kd11 kd12 kd13 kd14 kd15 ks4 kd16 kd17 kd18 kd19 kd20 ks5 kd21 kd22 kd23 kd24 kd25 ks6 kd26 kd27 kd28 kd29 kd30 ks7/p3 kd31 kd32 kd33 kd34 kd35 kd1 to kd10 are all set to 0 when the output pins ks1/p1 and ks2/p2 are set as general-purpose output ports with the "set key scan output port/general-purpose output port state" instruction and a key matrix of maximum 25 keys is formed from the output pins ks3 to ks6 and ks7/p3 and the input pins ki1 to ki5. (2) sa: sleep acknowledge data this output data bit is set to the state when the key was pr essed. also, while do will be low in this case, if serial data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. sa will be 1 in sleep mode and 0 in normal mode. x: don?t care output data ce a3 a2 a1 a0 b3 b2 b1 b0 kd2 kd1 xx kd35 0 1 0 0 0 0 1 1 do di cl sa x x kd34 ce a3 a2 a1 a0 b3 b2 b1 b0 kd3 kd2 kd1 xx x x x sa 0 1 0 0 0 0 1 1 do di cl kd35 x: don?t care output data LC75812PT no.a1417-30/54 key scan operation functions (1) key scan timing the key scan period is 2296t(s). to reliably determine the on/off state of the keys, the LC75812PT scans the keys twice and determines that a key has been pressed when the key data agrees. it outputs a key data read request (a low level on do) 4800t(s) after starting a key scan. if the key da ta dose not agree and a key was pressed at that point, it scans the keys again. thus the LC75812PT cannot detect a key press shorter than 4800t(s). note: * 22. not that the high/low states of these pins are determin ed by the "set key scan output port/general-purpose output port state" instruction, and that key scan output signals are not output from pins that are set to low. (2) in normal mode ? the pins ks1 to ks7 are set to high or low with the "set key scan output port/general-purpose output port state" instruction. ? if a key on one of the lines corresponding to a ks1 to ks7 pin which is set high is pressed, a key scan is started and the keys are scanned until all keys are released. mu ltiple key presses are recognized by determining whether multiple key data bits are set. ? if a key is pressed for longer than 4800t(s) (where t=1/fosc, t=1/f ck ) the LC75812PT outputs a key data read request (a low level on do) to the controller. the controller acknowledges this request and reads the key data. however, if ce is high during a serial data transfer, do will be set high. ? after the controller reads the key data, the key data read request is cleared (do is set high) and the LC75812PT performs another key scan. also note that do, being an open-drain output, requires a pull-up resistor (between 1k and 10k ). key scan t= t= key data read request key data read do di serial data transfer key address (43h) key address serial data transfer serial data transfer ce key input 2 key input 1 4800t[s] 4800t[s] 4800t[s] 1 fosc key address key data read request key data read request key data read key data read 1 f ck key on 4592t[s] *22 *22 *22 *22 *22 *22 *22 *22 *22 *22 *22 1 1 2 2 3 3 4 4 5 5 6 6 ks4 ks5 ks6 ks3 ks2 *22 ks1 *22 *22 7 7 ks7 t= 1 fosc t= f ck 1 LC75812PT no.a1417-31/54 (3) in sleep mode ? the pins ks1 to ks7 are set to high or low with the "set key scan output port/general-purpose output port state" instruction. ? if a key on one of the lines corresponding to a ks1 to ks7 pin which is set high is pressed in the rc oscillator operating mode, the oscillator on the osc pin is started (the ic starts receiving the extern al clock in external clock operating mode) and a key scan is performed . keys are scanned until all keys released. multiple key presses are recognized by determining whether multiple key data bits are set. ? if a key is pressed for longer than 4800t(s) (where t=1/fosc, t=1/f ck ) the LC75812PT outputs a key data read request (a low level on do) to the controller. the controller acknowledges this request and reads the key data. however, if ce is high during a serial data transfer, do will be set high. ? after the controller reads the key data, the key data read request is cleared (do is set high) and the LC75812PT performs another key scan. however, this dose not clear sleep mode. also note that do, being an open-drain output, requires a pull-up resistor (between 1k and 10k ). ? sleep mode key scan example example: when a "display on/off cont rol (sp=1)" instruction and a "set ke y scan output por t/general-purpose output port state (kp1 to kp3=0, kc1 to kc6= 0, kc7=1)" instruction are executed. (i.e. sleep mode with only ks7 high.) note: * 23. these diodes are required to reliably recognize multiple key presses on the ks7 line when sleep mode state with only ks7 high, as in the above example. that is, these diodes prevent incorrect operations due to sneak currents in the ks7 key scan output signal when keys on the ks1 to ks6 lines are pressed at the same time. multiple key presses although the LC75812PT is capable of key scanning without inserting diodes for dual key presses, triple key presses on the ki1 to ki5 input pin lines, or multiple key presses on the ks1 to ks7 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. therefore, a diode must be inserted in series with each key. app lications that do not recognize multiple key presses of three or more keys should check the key data for three or more 1 bits and ignore such data. key data read request key data read do di key address (43h) serial data transfer ce key scan key input (ks7 line) 4800t[s] 4800t[s] t= 1 fosc serial data transfer serial data transfer key address key data read request key data read t= 1 f ck when any one of these keys is pressed in rc oscillator operating mode, the oscillator on the osc pin is started (the ic starts receiving the external clock in external clock operating mode) and the keys are scanned. ki1 ki2 ki3 ki4 ki5 *23 ?l? ks4 ?h? ks7 ?l? ks3 ?l? ks2 ?l? ks5 ?l? ks6 ?l? ks1 LC75812PT no.a1417-32/54 1/8 duty, 1/4 bias drive technique when a "set display technique" instruction with fc0 = 0, fc 1 = 0 are executed: f8 = , f8 = when a "set display technique" instruction with fc0 = 1, fc 1 = 0 are executed: f8 = , f8 = when a "set display technique" instruction with fc0 = 0, fc 1 =1 are executed: f8 = , f8 = fosc 3072 fosc 1536 f ck 3072 f ck 1536 v lcd 3 v lcd 4 v lcd 4 v lcd 2 v lcd 1 v lcd 0 v lcd 4 v lcd 3 v lcd 3 v lcd 2 v lcd 2 v lcd 1 v lcd 1 v lcd 0 v lcd 0 com8 com2 com1 lcd driver output when only lcd segments corresponding to com2 are turned on lcd driver output when only lcd segments corresponding to com1 are turned on v lcd 4 v lcd 3 v lcd 2 v lcd 1 v lcd 0 v lcd 4 v lcd 3 v lcd 2 v lcd 1 v lcd 0 v lcd 4 v lcd 3 v lcd 2 v lcd 0 t8 t8 8 v lcd 4 v lcd 3 v lcd 2 v lcd 1 v lcd 0 1 f8 t8= v lcd 1 lcd driver output when all lcd segments corresponding to com1 to com8 are turned off lcd driver output when all lcd segments corresponding to com1 to com8 are turned on fosc 768 f ck 768 LC75812PT no.a1417-33/54 1/9 duty, 1/4 bias drive technique v lcd 3 v lcd 4 v lcd 4 v lcd 2 v lcd 1 v lcd 0 v lcd 4 v lcd 3 v lcd 3 v lcd 2 v lcd 2 v lcd 1 v lcd 1 v lcd 0 v lcd 0 com9 com2 com1 v lcd 4 v lcd 3 v lcd 2 v lcd 1 v lcd 0 v lcd 4 v lcd 3 v lcd 2 v lcd 1 v lcd 0 v lcd 4 v lcd 3 vlcd2 v lcd 1 v lcd 0 v lcd 4 v lcd 3 v lcd 2 v lcd 1 v lcd 0 t9 t9 9 1 f9 t9= lcd driver output when only lcd segments corresponding to com2 are turned on lcd driver output when only lcd segments corresponding to com1 are turned on lcd driver output when all lcd segments corresponding to com1 to com9 are turned off lcd driver output when all lcd segments corresponding to com1 to com9 are turned on when a "set display technique" instruction with fc0 = 0, fc 1 = 0 are executed: f9 = , f9 = when a "set display technique" instruction with fc0 = 1, fc 1 = 0 are executed: f9 = , f9 = when a "set display technique" instruction with fc0 = 0, fc 1 =1 are executed: f9 = , f9 = fosc 3456 fosc 1728 f ck 3456 f ck 1728 fosc 864 f ck 864 LC75812PT no.a1417-34/54 pwm output waveform tp= "set key scan output port/general-purpos e output port state" instruction data w10 w11 w12 w13 w14 w15 w20 w21 w22 w23 w24 w25 w30 w31 w32 w33 w34 w35 pwm output waveform of general-purpose output ports p1 to p3 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 0 1 0 2 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 3 "set key scan output port/general-purpos e output port state" instruction data pf0 pf1 pf2 pf3 pwm output waveform frame frequency fp[hz] 0 0 0 0 fosc/1536, fck/1536 1 0 0 0 fosc/1408, fck/1408 0 1 0 0 fosc/1280, fck/1280 1 1 0 0 fosc/1152, fck/1152 0 0 1 0 fosc/1024, fck/1024 1 0 1 0 fosc/896, fck/896 0 1 1 0 fosc/768, fck/768 1 1 1 0 fosc/640, fck/640 0 0 0 1 fosc/512, fck/512 1 0 0 1 fosc/384, fck/384 0 1 0 1 fosc/256, fck/256 (32/64) tp (56/64) tp p1 v dd v ss (48/64) tp p2 v ss v dd (40/64) tp p3 v ss v dd 1 (32/64) tp p1 v dd v ss (32/64) tp p2 v ss v dd (32/64) tp p3 v ss v dd 3 (8/64) tp (8/64) tp p1 v dd v ss (16/64) tp p2 v ss v dd (24/64) tp p3 v ss v dd 2 (16/64) tp (24/64) tp (32/64) tp (32/64) tp tp tp (56/64) tp (48/64) tp (40/64) tp 1 fp LC75812PT no.a1417-35/54 clock signal output waveform "set key scan output port/ general-purpose port state" instruction data pc30 pc31 pc32 general-purpose port p3 clock signal frequency fc (=1/tc) [hz] 1 1 0 clock signal output (fosc/2, f ck /2) 0 0 1 clock signal output (fosc/8, f ck /8) voltage detection type reset circuit (v det ) this circuit generates an output signal and resets the sy stem when logic block power is first applied and when the voltage drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage v det ,which is 2.2v, typical. to assure that this function operates reliably, a capacitor must be added to the logic block power supply line so that the logic block power supply voltage v dd rise time when the logic block power is first applied and the logic block power supply voltage v dd fall time when the voltage drops are both at least 1ms. (see figure 5.) power supply sequence the following sequences must be observed when power is turned on and off. (see figure 5.) ? power on: logic block power supply(v dd ) on lcd driver block power supply (v lcd ) on ? power off: lcd driver block power supply(v lcd ) off logic block power supply (v dd ) off when 5v signal is applied to the ce, cl, di, and inh pins which are to be connected to the controller and if the logic block power supply (v dd ) is off, set the input voltage at the ce, cl , di, and inh pins to 0v and apply the 5v signal to these pins after turning on the logic block power supply (v dd ). system reset 1. reset function the LC75812PT performs a system reset with the v det . when a system reset is applied, the display is turned off, key scanning is disabled, the key data is reset, and the general-purpose output ports are set to and held at the low level (v ss ). these states that are created as a result of the system rese t can be cleared by executing the instruction described below. (see figure 5.) ? clearing the display off state display operation can be enabled by executing a ?display on/off control? instruction. however, since the contents of the dcram, adram, and cgram are undefined, applications must set the contents of these memories before turning on display with the ?display on/off control? instruction. that is, applications must execute the following instructions. ? set display technique (the "set display technique" instruction must be executed first.) ? dcram data write ? adram data write (if the adram is used.) ? cgram data write (if the cgram is used.) ? set ac address ? set display contrast (if the display contrast adjustment circuit is used.) after executing the above instructions, applications must turn on the display with a ?display on/off control? instruction. note that when applications turn off in the normal mode, applications must turn off the display with a ?display on/off control? instruction or the inh pin. p3 tc tc/2 1 fc tc= LC75812PT no.a1417-36/54 ? clearing the key scan disable and key data reset states by executing the following instructions no t only create a state in which key scanni ng can be performed, but also clear the key data reset. ? set display technique (the "set display technique" instruction must be executed first.) ? set key scan output port/general-purpose output port state ? clearing the general-purpose output ports locked at the low level (v ss ) state by executing the following instructions clear the gene ral-purpose output ports locked at the low level (v ss ) state and set the states of the general-purpose output ports. ? set display technique (the "set display technique" instruction must be executed first.) ? set key scan output port/general-purpose output port state [figure 5] ? t1 1 [ms] (logic block power supply voltage v dd rise time) ? t2 0 ? t3 0 ? t4 1 [ms] (logic block power supply voltage v dd fall time) ? initial state settings set display technique (the "set display technique" instruction must be executed first.) dcram data write adram data write (if the adram is used.) cgram data write (if the cgram is used.) set ac address set display contrast (if the display contrast adjustment circuit is used.) ?set display technique? and ?set key scan output port/ general-purpose output port state? instruction execution ?display on/off control? instruction execution (turning the display on) ?display on/off control? instruction execution (turning the display off) v det v det t3 t4 t1 t2 key scan display state instruction execution v dd v lcd initial state settings display off display on can be set to such states as high (v dd ), or low (v ss ) level fixed at the low level (v ss ) display off execution enabled disabled general-purpose output ports LC75812PT no.a1417-37/54 2. block states during a system reset (1) clock generator,timing generator when a reset is applied, these circuits are forcibly in itialized internally. then, when the "set display technique" instruction is executed, oscillation of the osc pin starts in rc oscillator oper ating mode (the ic starts receiving the external clock in external clock operating mode), execution of the instruction is enabled. (2) instruction register, instruction decoder when a reset is applied, these circuits are forcibly initia lized internally. then, when instruction execution starts, the ic operates according to those instructions. (3) address register, address counter when a reset is applied, these circuits are forcibly initialized internally. then, the dcram and the adram addresses are set when ?set ac ad dress? instruction is executed. (4) dcram, adram, cgram since the contents of the dcram, adram, and cgram b ecome undefined during a reset, applications must execute ?dcram data write?, ?adram data write (if th e adram is used.)?, and ?c gram data write (if the cgram is used.)? instructions before executing a ?display on/off control? instruction. (5) cgrom character patterns are st ored in this rom. (6) latch although the value of the data in the latch is undefi ned during a reset, the adram, cgrom, and cgram data is stored by executing a ?display on/off control? instruction. (7) common driver, segment driver these circuits are forced to the displa y off state when a reset is applied. (8) contrast adjuster display contrast adjustment circuit oper ation is disabled when a reset is applied. after that, the display contrast can be set by executing a ?set display contrast? instruction. (9) key scan, key buffer when a reset is applied, these circuits are forcibly initia lized internally, and key scan operation is disabled. also, the key data is all set to 0. after that, key scanning can be performed by executing a "set key scan output port/general-purpose output port state" instruction. (10) general purpose port when a reset is applied, the general-purpose output port state is locked at the low level (v ss ). (11) ccb interface, shift register these circuits go to the serial data input wait state. LC75812PT no.a1417-38/54 (3) output pin states during the reset period output pin state during reset s1 to s64 s65/com9 com1 to com8 ks1/p1, ks2/p2 ks3 to ks6 ks7/p3 osc do l (v lcd 4) l (v lcd 4) *24 l (v lcd 4) l (v ss ) *25 l (v ss ) l (v ss ) *25 z (high-impedance) *26 h *27 * 24 this output pin is forcibly set to the segment output function and held low (v lcd 4). if the "set display technique" instruction is executed, however, eith er segment output or common output is selected according to the instruction. * 25 this output pin is forcibly set to general-purpose output port and held low (v ss ). if the ?set display technique? and the "set key scan output port/general-pur pose output port state" instructions ar e executed, however, either key scan output port or general-purpose output port is selected according to the instructions. * 26 this i/o pin is forcibly set to the high-impedance state. * 27 since this output pin is an open-drain output, a pull-up resistor (between 1k and 10k ) is required. this pin is held at the high level even if a key data read operation is performed before executing the "set display technique" or "set key scan output port/general-purpose output port state" instruction. blocks that are reset s65/com9 s64 v lcd 2 adram 65 bits cgram 5 8 16 bits vdet clock generator contrast adjuster timing generator address register instruction register common driver instruction decoder address counter dcram 52 8 bits cgrom 5 8 240 bits shift register latch segment driver osc inh do di p1/ks1 p2/ks2 ks3 ks4 ks6 ce ki1 ki2 ki3 ki4 ki5 cl s1 s63 com8 com1 key buffer ccb interface key scan v dd v lcd 4 v lcd 3 v lcd 1 v lcd v lcd 0 v ss test general purpose port p3/ks7 ks5 LC75812PT no.a1417-39/54 osc pin peripheral circuit (1) rc oscillator operating mode (when the "set display technique (oc=0)" instruction is executed) when rc oscillator operating mode is selected, an external resistor rosc and an external capacitor cosc must be connected between the osc pin and gnd. (2) external clock operating mode (when the "set display technique (oc=1)" instruction is executed) when selecting the external clock operating mode, connect a current protection resistor rg (2.2 to 22k ) between the osc pin and external clock output pin (external oscillato r). determine the value of the resistance according to the maximum allowable current value at the external clock output pin. also make sure that the waveform of the external clock is not heavily distorted. note: * 28. allowable current value at external clock output pin > pins p1 to p3 peripheral circuit it is recommended that the following circuit be used when adjusting the brightness of the led backlight in pwm mode using the general-purpose output ports p1 to p3 (when pwm signal output function is selected with the general-purpose output ports p1 to p3 under the "set key scan output port/general-purpose output port state" instruction): note when applying a 5v signal to the ce, cl, di, and inh pins when applying a 5v signal to the ce, cl, di, and inh pins which are to be connected to the controller, set the input voltage to the ce, cl, di, and inh pins to 0v if the logic block power supply (v dd ) is off, and apply the 5v signal to those pins after turning on the logic block power supply (v dd ). osc cosc rosc osc external clock output pin rg external oscillator v dd rg led v cc p1 to p3 LC75812PT no.a1417-40/54 sample application circuit 1 1/8 duty, 1/4 bias drive technique (for use with normal panels) note * 29. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the LC75812PT is reset by the v det . * 30. if a variable resistor is not used for display contrast fine adjustment, the v lcd 4 pin must be connected to ground. * 31. in rc oscillator operating mode, an external resistor, rosc, and an external capacitor, cosc, must be connected between the osc pin and ground. when sel ecting the external clock operating mode, connect a current protection resistor rg (2.2 to 22k ) between the osc pin and the external clock output pin (external oscillator). (see the ?osc pin peripheral circuit? section.) * 32. if the function of inh pin is not used, the inh pin must be connected to the logic block power supply v dd . * 33. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1k and 10k ) appropriate for the capacitance of the external wi ring so that signal wave forms are not degraded. * 34 when applying a 5v signal to the ce, cl, di, and inh pins, set the input voltage to 0v if the logic block power supply (v dd ) is off and apply the 5v signal to those pins after turning on the logic block power supply (v dd ). to the controller power supply to the controller from the controller lcd panel general-purpose output ports used with the backlight controller or other circuit key matrix (up to 35 keys) com8 com7 com6 com5 com4 com3 com2 com1 c c c c 0.047 f +8v *29 +3.3v inh *32 ce cl *33 do di v lcd 4 *30 v lcd 3 v lcd 2 v lcd 1 open v lcd v lcd 0 v ss test v dd com9/s65 s64 s63 s62 s61 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 osc *31 *34 p 1 / k s 1 p 2 / k s 2 k s 3 k s 4 k s 5 k s 6 k i 1 k i 2 k i 3 k i 4 k i 5 p 3 / k s 7 LC75812PT no.a1417-41/54 sample application circuit 2 1/8 duty, 1/4 bias drive technique (for use with large panels) note * 29. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the LC75812PT is reset by the v det . * 30. if a variable resistor is not used for display contrast fine adjustment, the v lcd 4 pin must be connected to ground. * 31. in rc oscillator operating mode, an external resistor, rosc, and an external capacitor, cosc, must be connected between the osc pin and ground. when sel ecting the external clock operating mode, connect a current protection resistor rg (2.2 to 22k ) between the osc pin and the external clock output pin (external oscillator). (see the ?osc pin peripheral circuit? section.) * 32. if the function of inh pin is not used, the inh pin must be connected to the logic block power supply v dd . * 33. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1k and 10k ) appropriate for the capacitance of the external wi ring so that signal wave forms are not degraded. * 34 when applying a 5v signal to the ce, cl, di, and inh pins, set the input voltage to 0v if the logic block power supply (v dd ) is off and apply the 5v signal to those pins after turning on the logic block power supply (v dd ). com8 com7 com6 com5 com4 com3 com2 com1 r r r r c c c c 0.047 ? r 2.2k +8v *29 +3.3v ce cl *33 do di v lcd 4 *30 v lcd 3 v lcd 2 v lcd 1 v lcd v lcd 0 v ss test v dd com9/s65 s64 s63 s62 s61 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 osc *31 *34 p 1 / k s 1 p 2 / k s 2 k s 3 k s 4 k s 5 k s 6 k i 1 k i 2 k i 3 k i 4 k i 5 p 3 / k s 7 inh *32 to the controller power supply to the controller from the controller lcd panel general-purpose output ports used with the backlight controller or other circuit key matrix (up to 35 keys) LC75812PT no.a1417-42/54 sample application circuit 3 1/9 duty, 1/4 bias drive technique (for use with normal panels) note * 29. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the LC75812PT is reset by the v det . * 30. if a variable resistor is not used for display contrast fine adjustment, the v lcd 4 pin must be connected to ground. * 31. in rc oscillator operating mode, an external resistor, rosc, and an external capacitor, cosc, must be connected between the osc pin and ground. when sel ecting the external clock operating mode, connect a current protection resistor rg (2.2 to 22k ) between the osc pin and the external clock output pin (external oscillator). (see the ?osc pin peripheral circuit? section.) * 32. if the function of inh pin is not used, the inh pin must be connected to the logic block power supply v dd . * 33. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1k and 10k ) appropriate for the capacitance of the external wi ring so that signal wave forms are not degraded. * 34 when applying a 5v signal to the ce, cl, di, and inh pins, set the input voltage to 0v if the logic block power supply (v dd ) is off and apply the 5v signal to those pins after turning on the logic block power supply (v dd ). s65/com9 com8 com7 com6 com5 com4 com3 com2 com1 c c c c 0.047 LC75812PT no.a1417-43/54 sample application circuit 4 1/9 duty, 1/4 bias drive technique (for use with large panels) note * 29. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the LC75812PT is reset by the v det . * 30. if a variable resistor is not used for display contrast fine adjustment, the v lcd 4 pin must be connected to ground. * 31. in rc oscillator operating mode, an external resistor, rosc, and an external capacitor, cosc, must be connected between the osc pin and ground. when sel ecting the external clock operating mode, connect a current protection resistor rg (2.2 to 22k ) between the osc pin and the external clock output pin (external oscillator). (see the ?osc pin peripheral circuit? section.) * 32. if the function of inh pin is not used, the inh pin must be connected to the logic block power supply v dd . * 33. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1k and 10k ) appropriate for the capacitance of the external wi ring so that signal wave forms are not degraded. * 34 when applying a 5v signal to the ce, cl, di, and inh pins, set the input voltage to 0v if the logic block power supply (v dd ) is off and apply the 5v signal to those pins after turning on the logic block power supply (v dd ). s65/com9 com8 com7 com6 com5 com4 com3 com2 com1 r r r r c c c c 0.047 ? r 2.2k +8v *29 +3.3v ce cl *33 do di v lcd 4 *30 v lcd 3 v lcd 2 v lcd 1 v lcd v lcd 0 v ss test v dd s64 s63 s62 s61 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 osc *31 *34 p 1 / k s 1 p 2 / k s 2 k s 3 k s 4 k s 5 k s 6 k i 1 k i 2 k i 3 k i 4 k i 5 p 3 / k s 7 inh *32 to the controller power supply to the controller from the controller lcd panel general-purpose output ports used with the backlight controller or other circuit key matrix (up to 35 keys) LC75812PT no.a1417-44/54 sample correspondence between instructions and the display (when the LC75812PT-8565 is used) lsb instruction (hexadecimal) msb no. d96 to d99 d100 to d103 d104 to d107 d108 to d111 d112 to d115 d116 to d119 display operation 1 power application (initialization with the v det ) initializes the ic. the display is in the off state. set display technique 2 0 8 sets to 1/8 duty 1/4 bias display drive technique dcram data write (normal increment mode) 3 0 2 0 0 1 a writes the display data ? ? to dcram address 00h dcram data write (normal increment mode) 4 3 5 writes the display data ?s? to dcram address 01h dcram data write (normal increment mode) 5 1 4 writes the display data ?a? to dcram address 02h dcram data write (normal increment mode) 6 e 4 writes the display data ?n? to dcram address 03h dcram data write (normal increment mode) 7 9 5 writes the display data ?y? to dcram address 04h dcram data write (normal increment mode) 8 f 4 writes the display data ?o? to dcram address 05h dcram data write (normal increment mode) 9 0 2 writes the display data ? ? to dcram address 06h dcram data write (normal increment mode) 10 c 4 writes the display data ?l? to dcram address 07h dcram data write (normal increment mode) 11 3 5 writes the display data ?s? to dcram address 08h dcram data write (normal increment mode) 12 9 4 writes the display data ?i? to dcram address 09h dcram data write (normal increment mode) 13 0 2 writes the display data ? ? to dcram address 0ah dcram data write (normal increment mode) 14 c 4 writes the display data ?l? to dcram address 0bh dcram data write (normal increment mode) 15 3 4 writes the display data ?c? to dcram address 0ch dcram data write (normal increment mode) 16 7 3 writes the display data ?7? to dcram address 0dh dcram data write (normal increment mode) 17 5 3 writes the display data ?5? to dcram address 0eh dcram data write (normal increment mode) 18 8 3 writes the display data ?8? to dcram address 0fh dcram data write (normal increment mode) 19 1 3 writes the display data ?1? to dcram address 10h dcram data write (normal increment mode) 20 2 3 writes the display data ?2? to dcram address 11h dcram data write (normal increment mode) 21 0 2 0 a writes the display data ? ? to dcram address 12h continued on next page. LC75812PT no.a1417-45/54 continued from preceding page. lsb instruction (hexadecimal) msb no. d96 to d99 d100 to d103 d104 to d107 d108 to d111 d112 to d115 d116 to d119 display operation set ac address 22 0 0 0 2 loads the dcram address 00h and the adram address 0h into ac display on/off control 23 f f f 1 1 4 turns on the lcd for all digits (13 digits) in mdata display shift 24 1 c shifts the display (mdata only) to the left display shift 25 1 c shifts the display (mdata only) to the left display shift 26 1 c shifts the display (mdata only) to the left display shift 27 1 c shifts the display (mdata only) to the left display shift 28 1 c shifts the display (mdata only) to the left display shift 29 1 c shifts the display (mdata only) to the left display on/off control 30 0 0 0 0 8 4 set to sleep mode, turns off the lcd for all digits display on/off control 31 f f f 1 1 4 turns on the lcd for all digits (13 digits) in mdata set ac address 32 0 0 0 2 loads the dcram address 00h and the adram address 0h into ac * 35) the sample correspondence betw een the instructions and the display assumes the use of 13 digits 1 row 5 7 dot matrix lcd. neither cgram nor adram are used. s a n y o l s i l c sanyo lsi lc7 anyo lsi lc75 nyo lsi lc758 yo lsi lc7581 o lsi lc75812 lsi lc75812 lsi lc75812 s a n y o l s i l c LC75812PT no.a1417-46/54 * 36) given below are the data formats of the "dcram data write" instructions (no. 3 to no. 21) for the sample correspondence between the instructions and the display executed in the super increment mode. in the super increment mode processing example shown below, 19 characters of dcram data is divided and written into dcram in two operations. instruction (hex) lsb msb no. d0 to d3 d4 to d7 d8 to d11 d12 to d15 d16 to d19 d20 to d23 d24 to d27 d28 to d31 d32 to d35 d36 to d39 d40 to d43 d44 to d47 dcram data write (super increment mode) 3 to 15 0 2 3 5 1 4 e 4 9 5 f 4 dcram data write (super increment mode) 16 to 21 instruction (hex) lsb msb no. d48 to d51 d52 to d55 d56 to d59 d60 to d63 d64 to d67 d68 to d71 d72 to d75 d76 to d79 d80 to d83 d84 to d87 d88 to d91 d92 to d95 dcram data write (super increment mode) 3 to 15 0 2 c 4 3 5 9 4 0 2 c 4 dcram data write (super increment mode) 16 to 21 7 3 5 3 8 3 1 3 2 3 instruction (hex) lsb msb no. d96 to d99 d100 to d103 d104 to d107 d108 to d111 d112 to d115 d116 to d119 operation dcram data write (super increment mode) 3 to 15 3 4 0 0 2 a display data ? ? ?s? ?a? ?n? ?y? ?o? ? ? ?l? ?s? ?i? ? ? ?l? ?c? are written sequentially to dcram addresses 00h to 0ch. dcram data write (super increment mode) 16 to 21 0 2 d 0 2 a display data ?7? ?5? ?8? ?1? ?2? ? ? are written sequentially to dcram addresses 0dh to 12h. LC75812PT no.a1417-47/54 notes on the controller key data read techniques 1. timer based key data acquisition ? flowchart ? timing chart t5: key scan execution time when the key data agreed for two key scans. (4800t(s)) t6: key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (9600t(s)) t7: key address (4 3h) transfer time t8: key data read time ? explanation in this technique, the controller uses a timer to determ ine key on/off states and read the key data. the controller must check the do state when ce is low every t9 period without fail. if do is low, the controller recognizes that a key has been pressed and executes the key data read operation. the period t9 in this technique must satisfy the following condition. t9>t6+t7+t8 when key data read operation is executed with do set hi gh (no key data read request present), the key data (kd1 to kd35) and sleep acknowle dge data (sa) are invalid. key data read processing yes no do=?l? ce=?l? controller determination (key on) controller determination (key on) controller determination (key off) controller determination (key on) controller determination (key off) key data read request key data read do di ce key on key on key address key scan key input t6 t9 t9 t9 t9 t5 t8 t8 t7 t7 t5 t7 t8 t5 1 fosc t= 1 f ck t= LC75812PT no.a1417-48/54 2. interrupt based key data acquisition ? flowchart ? timing chart t5: key scan execution time when the key data agreed for two key scans. (4800t(s)) t6: key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (9600t(s)) t7: key address (4 3h) transfer time t8: key data read time ? explanation in this technique, the controller uses interrupts to determine key on/off states and read the key data. the controller must check the do state when ce is low. if do is low, the controller recognizes that a key has been pressed and executes the key data read operation. after that the next key on/off determination is performed after the time t10 has elapsed by checking the do state when ce is low and reading the key data. the period t10 in this technique must satisfy the following condition. t10 > t6 when key data read operation is executed with do set hi gh (no key data read request present), the key data (kd1 to kd35) and sleep acknowle dge data (sa) are invalid. key data read processing yes yes no do=?l? ce=?l? wait for at least t10 key off ce=?l? no do=?h? controller determination (key off) key on key on key scan controller determination (key on) controller determination (key off) controller determination (key on) controller determination (key on) controller determination (key on) key data read request key data read do di ce key address key input t10 t10 t10 t10 t5 t6 t8 t8 t7 t7 t5 t7 t8 t5 t7 t8 1 fosc t= 1 f ck t= LC75812PT no.a1417-49/54 about data communication me thod with the controller 1. about data communication method of 4 line type ccb format the 4 line type ccb format is the data communication method of before. the LC75812PT must connect to the controller as followings. 2. about data communication method of 3 line type ccb format the 3 line type ccb format is the data communication method that made a common use of the data input di in the data output do. the LC75812PT must connect to the controller as followings. in this case, applications must transfer the data comm unication start command before the serial data input (ccb address ?42h?, display data and control da ta transfer) or serial data output ( ccb address ?43h? transfer, key data read) to avoid the collision of the data input signal di and the data output signal do. then applications must transfer the data communication stop command when the controller wants to detect the key data read request signal (a low level on do) during a movement stop of the serial data input and the serial data output. < 1 > data communication start command (1) when cl is stoped at the low level (2 ) when cl is stoped at the high level < 2 > data communication stop command (1) when cl is stoped at the low level (2 ) when cl is stoped at the high level note: *37. connect the pull-up resistor rup. select a resistance (between 1 to 10k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *38. the (int) pin is an input port for the key data read request signal (a low level on do) detection. do di cl ce di do cl ce rup LC75812PT controller (int) *38 *37 note: *37. connect the pull-up resistor rup. select a resistance (between 1 to 10k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *38. the (int) pin is an input port for the key data read request signal (a low level on do) detection. do di cl ce dio cl ce rup LC75812PT controller (int) *37 *38 0 0 0 0 1 ccb address ?00h? di/do cl ce 0 0 0 0 0 0 1 1 1 1 0 command data 0 0 0 01 di / do cl ce 0 0 00 0 011 1 1 0 ccb address ?00h? command data 1 1 0 0 1 di/do cl ce 0 0 0 0 0 0 1 1 0 0 0 ccb address ?00h? command data 1 1 0 01 di / do cl ce 0 0 00 0 011 0 0 0 ccb address ?00h? command data LC75812PT no.a1417-50/54 data communication flowchart of 4 li ne type or 3 line type ccb format 1. flowchart of the initial setting when power is turned on. 2. flowchart of the serial data input 3. flowchart of the serial data output data communication start command transfer serial data output (key data and sleep acknowledge data read) the controller acknowledges the key data read request (when the ce is low, the do is low) yes no note: *40. in the case of the 4 line type ccb format, the transfer of data communication start command is unnecessary, and, in the case of the 3 line type ccb format, the transfer is necessary. *41. because the serial data output has the role of the data communication stop command, it is not necessary to transfer the data communication stop command some other time. *40 *41 data communication start command transfer yes serial data input (execute instructions) data communication stop command transfe r the controller wants to detect the key data read request signal ( a low level on do ) . no *39 *39 note: *39. in the case of the 4 line type ccb format, the transfers of data communication start command and data communication stop command are unnecessary, and, in the case of the 3 line type ccb format, these transfers are necessary. power on (applications must observe that the power supply v dd rise time is at least 1ms.) serial data input (execute instructions) power supply stability (applications must wait till the level of the power supply is stable) system reset clear (display on, key scanning is enabled, general-purpose output port state setting are enabled) note: the flowchart for power-on time initialization is the same for the 4- and 3-wire ccb formats. see "power supply sequence" and "system reset." LC75812PT no.a1417-51/54 timing chart of 4 line type and 3 line type ccb format 1. timing chart of 4 line type ccb format < example 1 > < example 2 > < example 3 > note: * 42. when the key data agrees for two key scans, the key scan execution time is 4800t[s]. and, when the key data does not agree for two key scans and the key scan is executed again, the key scan exec ution time is 9600t[s]. di ce key on key off key scan key input serial data input (execute instructions) serial data output (key data read) key data read request key data read request key scan execution *42 do ccb address (42h) ccb address (42h) ccb address (42h) ccb address (43h) key scan execution *42 di ce key on key scan key input serial data input (execute instructions) serial data output (key data read) key data read request key data read request key on key off key off do serial data output (key data read) key scan execution *42 key scan execution *42 ccb address (42h) ccb address (42h) ccb address (42h) ccb address (43h) ccb address (43h) di ce key on key scan key input serial data input (execute instructions) serial data output (key data read) key data read request key data read request key off serial data output (key data read) key off do key scan execution *42 key scan execution *42 ccb address (42h) ccb address (42h) ccb address (42h) ccb address (43h) ccb address (43h) 1 fosc t= f ck t= 1 LC75812PT no.a1417-52/54 2. timing chart of 3 line type ccb format < example 1 > < example 2 > < example 3 > note: * 42. when the key data agrees for two key scans, the key scan execution time is 4800t[s]. and, when the key data does not agree for two key scans and the key scan is executed again, the key scan exec ution time is 9600t[s]. di/do ce key on key off key scan key input data communication start command serial data input (execute instructions) data communication stop command data communication start command serial data output (key data read) key data read request key data read request ccb address (42h) key scan execution *42 key scan execution *42 ccb address (42h) ccb address (42h) ccb address (43h) di/do ce key on key scan key input data communication start command serial data input (execute instructions) data communication stop command data communication start command serial data output (key data read) key data read request key data read request key on key off key off data communication start command serial data output (key data read) key scan execution *42 key scan execution *42 ccb address (42h) ccb address (42h) ccb address (42h) ccb address (43h) ccb address (43h) di/do ce key on key scan key input data communication start command serial data input (execute instructions) serial data output (key data read) key data read request key data read request key off serial data output (key data read) key off key scan execution *42 key scan execution *42 ccb address (42h) ccb address (42h) ccb address (43h) ccb address (43h) ccb address (42h) data communication start command 1 fosc t= f ck t= 1 LC75812PT no.a1417-53/54 LC75812PT-8565 character font (standard) ? a ? ? ? ? ? ? ? ? ? ? s s ? ? ? a n e ? a ? ? ? ? ? ? ? ? ? o n g i ij g i i j p q r s t u v w x y z a b c d e f g h i j k l m n o p q r s t u v w x y z [ _ ] 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0@ a b c d e f g h i j k l m n o 1 2 3 4 5 6 7 8 9 : ; < = > ? ! # $ % & ( ) * , . / cg ram(1) (16) (15) (14) (13) (12) (11) (10) (9) (8) (7) (6) (5) (4) (3) (2) 0 0 0 1 0 0 0 0 lsb 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 msb 0 0 0 0 upper 4bit lower 4bit LC75812PT no.a1417-54/54 ps on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner. |
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